MTS Design Architect-Custom Layout, HBM

Req ID:

JR116186 MTS Design Architect-Custom Layout, HBM

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

As an HBM Design Architect-Custom Layout Lead, you will support the development of advanced analog, mixed‑signal, and digital circuits as well as full‑chip integration for next‑generation High Bandwidth Memory (HBM) products. This role focuses on physical design and layout, including creating optimized floorplans, driving circuit placement and routing strategies, and delivering high‑quality block‑level layouts using advanced process nodes. You will collaborate closely with architecture, circuit build, and layout teams to enable groundbreaking DRAM solutions that push performance, power efficiency, and density for developing HBM technologies. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making.

Responsibilities

• Lead end-to-end layout execution of analog, mixed-signal, custom digital blocks and overall chip integration for HBM products.
• Own full-chip technical decisions covering analog, digital, memory, ESD, EM/IR and ensure effective performance, power, and area (PPA).
• Technical Expertise: Hands-on experience in layout develop of critical Memory /Analog and mixed-signal blocks such as: Array Layout, Decoder, Control logic, IOs, PLLs, ADCs, DACs, LDOs, Bandgaps, Reference Generators, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers.
• Collaborate with HBM architects and circuit designers on floorplanning, placement, routing, and integration strategies.
• Support integration of Memory, Logic, and Analog circuits for new HBM product architectures.
• Provide design-focused insights to improve circuit robustness, performance, and reliability.
• Participate in reviews and fixing issues across physical build, parasitic extraction, and full‑chip integration.

Qualifications

• MS degree with 8+ years of memory‑related custom layout design experience, or BS degree with 12+ years of relevant experience.
• Expertise with Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS.
• Strong understanding of analog layout fundamentals including matching, EM, latch‑up, coupling, IR‑drop, crosstalk, and parasitic impacts.
• Hands‑on experience developing analog and mixed‑signal layouts (e.g., sense amplifiers, LDOs, PLLs).
• Strong analytical, problem‑solving, and collaboration skills.
• Experince of leveraging AI to accelerate layout development.

Preferred Qualifications

• Experience working on DRAM custom layout.
• Ability to clearly communicate technical concepts to design, architecture, and verification teams.
• Motivated contributor who excels in team‑based, fast‑paced engineering environments.

Job Profile(s):

Systems Design Engineer 5 - Systems Design Engineering SMTS

Relocation Level: TBD

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