AI/ML Software Engineer (2026 New College Graduate)

We're looking for AI/ML Software Engineer to lead workload-driven architecture strategy across hardware and software boundaries. You will study, model, and optimize AI/ML workloads for current and next-generation products, align across HW and SW engineering organizations, and serve as a technical authority on performance and architecture tradeoffs. This is an individual contributor role with cross-functional scope and organizational influence.

Essential Responsibilities:

• Execute workload characterization and hardware performance analysis for AI/ML systems — selecting representative workloads, defining measurement methodology, building support for MIPS products (e.g., the S8200), and projecting system-level KPIs. Your findings will directly inform SoC architecture decisions, memory subsystem design, and HW/SW co-optimization strategy.
• Define the software frameworks across the product portfolio: what metrics matter, how to measure them accurately, how to estimate them pre-silicon, and how to use them to make architectural bets. Leverage and contribute to open-source infrastructure like MLIR and IREE to implement and validate this work.
• You will also represent software in architectural discussions with hardware teams (CPU, SoC, memory, interconnect) and software teams (compilers, runtimes, ML frameworks). Identify critical bottlenecks — compute throughput, DRAM bandwidth, on-chip memory, data movement latency, or software overhead — and build the case for specific architectural changes or optimization investments.
• Present findings and recommendations to senior engineering leadership and product stakeholders. You should be as comfortable writing a one-page architectural recommendation as a detailed technical memo.

• Expertise in open-source software, CPU and SoC architecture — memory hierarchies, out-of-order execution, vector/SIMD pipelines, power management — and how these interact with AI/ML workloads. Basic understanding of system-level memory bandwidth constraints (DDR/LPDDR bandwidth, latency, utilization efficiency) and the ability to reason quantitatively about memory-bound vs. compute-bound workloads.
• Knowledge of AI/ML acceleration on edge devices — NPUs, dedicated inference accelerators, DSP-based pipelines — and the HW/SW co-design challenges involved. Familiarity with model quantization, sparsity, or other efficiency techniques and their hardware interaction is a strong plus.
• Familiarity with AI compiler infrastructure: MLIR-based toolchains, IREE, TVM, TFLite, or equivalent. Understanding how graph representations are transformed, tiled, scheduled, and lowered to hardware will improve your ability to identify where compiler strategy and hardware architecture must be co-designed. Prior contributions to such toolchains are a significant differentiator.
• Effective cross-functional collaborator who can contribute to technical consensus, writes clearly, and calibrates technical depth for different audiences.

Preferred Qualifications: 

What Sets Strong Candidates Apart

• Knowledge of CPU hardware features such as vector extensions (AVX, NEON, RVV) or matrix extensions (AMX, SME)
• SoC architecture requirements from workload analysis
• Contributions to graph lowering in MLIR/IREE or similar compiler infrastructure
• Internal or external publications or contributions to technical standards
• Knowledge of RISC-V architecture and Vector/Matrix extensions

Other Requirements

• English fluency (written and verbal)
• Up to 10% travel
• US work authorization
• 100% in-office (Dallas, Austin, or San Jose)

Expected Salary Range

$86,000.00 - $148,000.00

The exact Salary will be determined based on qualifications, experience and location.