Hiring.Camp

Sr. ASIC Design Engineer

AMBARELLA

·

Aug 14, 2025

Apply
Salary
$135k – $170k
Location
US Headquarters, United States of America
Type
Full-time
Department
Engineering
Seniority
Senior
Source
Workday

Description

AI Vision Processors For Edge Applications

Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.

Job Description

Position Responsibilities:

  • Designing and implementing video compression, image processing, vector computation, and flexible compute systems optimized for future AI agents and large language model (LLM) inference—alongside processor cores and memory subsystems using System Verilog, with a focus on enabling next-generation edge AI markets such as automation, robotics, and intelligent low power embedded systems.
  • Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages.
  • Synthesize and optimize RTL for timing, area, and power.
  • Explore micro-architecture and architectural tradeoffs via quick modelling using scripting languages such as python, Perl etc.
  • Developing unit level test environments and tests cases
  • Developing front-end methodologies and tool flows.
  • Participating in chip bring-up and testing.
  • Analyzing and reviewing code coverage and functional coverage and providing recommendations to the verification team to address any gaps.

Requirements:

  • Master’s degree in electrical/Electronics/Computer Engineering with 0-5 years of experience.
  • Good understanding of computer architecture, logic design and VLSI design.
  • Knowledge of System Verilog, Verilog, python, and Perl.
  • Knowledge of design verification, and functional coverage.
  • Ability to program in scripting languages and the ability to write assembly language programs.
  • Strong communication skills and a good team player.
  • Adept problem-solving abilities
  • Knowledge of logic synthesis and timing closer is a plus

The base salary range is $135,000 - $170,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The successful candidate will have the opportunity to convert to a full-time regular position. We also offer new-hire RSU grants and the opportunity for annual RSU grants, as well as other highly competitive benefits.

Skills

PythonPerl

Similar Jobs

30

Sr ASIC Design Engineer - TeraWave

Blueorigin·Cupertino, California +1·Remote, Onsite

1d ago

Senior ASIC/FPGA Design Engineer

RTX·McKinney, Texas·Onsite

1d ago

Senior ASIC Design Engineer

"Cornelis Networks, Inc."·Remote

3d ago

Sr ASIC Design Engineer

Blueorigin·Pol, Galicia

3d ago

Senior ASIC Design Engineer

Astera Labs·Israel +1

4d ago

ASIC Design Senior Staff Engineer

Qualcomm·Shanghai, China

1w ago

Senior ASIC Design Verification Engineer - Slingshot

Hewlett Packard Enterprise (HP)·Bloomington, Minnesota +2·Hybrid

1w ago

Senior ASIC Design Verification Engineer - Slingshot

Hewlett Packard Enterprise (HP)·Bloomington, Minnesota +2·Hybrid

1w ago

Senior ASIC Design Verification Engineer - Slingshot

Hewlett Packard Enterprise (HP)·Bloomington, Minnesota +2·Hybrid

1w ago

ASIC RTL Design Engineer (Sr. Engr / Sr. Lead Engr)

Qualcomm·Bengaluru, Karnataka

1w ago

Senior VLSI ASIC Logic Design Engineer

Hewlett Packard Enterprise (HP)·Bloomington, Minnesota +3·Hybrid

1w ago

Senior VLSI ASIC Logic Design Engineer

Hewlett Packard Enterprise (HP)·Bloomington, Minnesota +3·Hybrid

1w ago

Senior ASIC Physical Design Engineering Technical Lead

Cisco·Austin, Texas +1·Onsite

1w ago

Senior VLSI ASIC Logic Design Engineer

Hewlett Packard Enterprise (HP)·Bloomington, Minnesota +3·Hybrid

1w ago

Senior VLSI ASIC Logic Design Engineer

Hewlett Packard Enterprise (HP)·Bloomington, Minnesota +3·Hybrid

1w ago

Senior VLSI ASIC Logic Design Engineer

Hewlett Packard Enterprise (HP)·Bloomington, Minnesota +3·Hybrid

1w ago

Senior VLSI ASIC Logic Design Engineer

Hewlett Packard Enterprise (HP)·Bloomington, Minnesota +3·Hybrid

1w ago

HW SOC/ASIC Physical Design Engineer, Senior/Staff (US Citizenship Required)

Qualcomm·San Diego, California·Onsite

1w ago

ASIC Design Verification Engineer (Security Group) - Sr Staff

Qualcomm·Santa Clara, California

2w ago

Senior Analog ASIC Design Engineer  

Ranovus·Nürnberg, Bavaria

2w ago

Senior ASIC Design Verification Engineer

Cisco·US·Onsite

2w ago

Senior ASIC Research Engineer – Front-end Digital Design

USC is·Arlington, Virginia

2w ago

Senior ASIC Design Verification Engineer - Slingshot

Hewlett Packard Enterprise (HP)·Bloomington, Minnesota +2·Remote, Hybrid

2w ago

Senior ASIC Design Verification Engineer - Slingshot

Hewlett Packard Enterprise (HP)·Bloomington, Minnesota +2·Remote, Hybrid

2w ago

Senior ASIC Design Verification Engineer - Slingshot

Hewlett Packard Enterprise (HP)·Bloomington, Minnesota +2·Remote, Hybrid

2w ago

Senior Engineer, ASIC Digital Design (System IP Verification)

Global Foundries·TWN - T'ai-wan - Hsinchu, Taiwan

2w ago

Senior Engineer-ASIC Design Verification

Micron Technology·Hyderabad, Telangana

2w ago

Senior Engineer-ASIC Design Verification

Micron·Hyderabad, Telangana

2w ago

Senior ASIC Design Engineer

Nvidia·Santa Clara, California·Hybrid, Onsite

3w ago

Senior ASIC Physical Design Engineer

Niobium

3w ago