FPGA Design Verification Engineer

Hello,

• FPGA Design Verification Engineer
• Client-Boeing 
• IP layer-  VDart
• Location: El Segundo, CA, onsite five days per week
• Employment Type: W-2 Contract
• Duration: 12 months
• Compensation: $60–$65 per hour
• Work Authorization: U.S. citizenship required
• Clearance: DoD Secret clearance preferred

Job Description: 

You will develop verification environments, validate hardware and software interactions, and work with architecture, design, and firmware teams to identify and resolve issues.
This role requires 8–15 years of relevant experience, strong hands-on SystemVerilog/UVM skills, and the ability to manage verification responsibilities independently.

Required Skill:

• 8–15 years of relevant FPGA design verification experience.
• Strong understanding of FPGA devices and verification methodologies.
• Hands-on experience developing SystemVerilog/UVM testbenches and reusable verification components.
• Experience developing C-based tests and integrating hardware/software verification flows.
• Experience with test planning, functional and code coverage, debugging, and coverage closure.
• Ability to work independently and collaborate across engineering teams.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent relevant experience.
• U.S. citizenship required.
• Ability to work onsite in El Segundo, CA, five days per week.

Preferred Qualifications

• DoD Secret clearance.
• Experience verifying SpaceWire protocols.
• Experience with DDR4 memory interfaces.
• Experience with SerDes connectivity.
• Experience with configuration, control, and telemetry systems.

Apply
Submit your resume highlighting your FPGA verification experience, SystemVerilog/UVM expertise, relevant interface or protocol experience, and availability for onsite work in El Segundo.