Senior Engineer II - Verification

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Job Description:

As a Senior PCIe Verification Engineer, you will work on verification environments for our next-generation Data Center Storage products, including enterprise-class PCIe Gen5/6/7 memory controllers and other PCIe/CXL-based SoC products. You will drive verification efforts with a strong focus on PCIE/CXL protocol behavior, ensuring robust, silicon-ready designs. These complex SoC silicon devices enable top-tier data centers across Next-Gen Storage, Artificial Intelligence, and High-Performance Computing market segments.

 

Job Responsibilities

• Define verification plans and build testbenches using UVM/System Verilog for PCIe Gen5/6/7 IP.
• Interpret PCIe protocol specifications to develop and execute verification plans in simulation environments.
• Integrate and configure third-party PCIe Verification IPs (e.g., Synopsys, Cadence) for Gen5/6/7 verification.
• Develop test cases, checkers, and functional/code coverage models per the verification plan.
• Collaborate with firmware, emulation, and silicon validation teams; support pre-silicon and post-silicon bring-up/debug.

Requirements/Qualifications:

• Bachelor's/master’s degree in Electronics/VLSI Engineering with 6+ years of RTL verification experience, including 2+ years specifically in PCIe protocol verification.
• Strong hands-on expertise in UVM/System Verilog-based testbench development
• Domain expertise in PCIe Gen5/6/7 protocols, focusing on Transaction Layer verification.
• Expertise in verifying PCIe features, including compliance verification on PCIe/CXL EP/RC.
• Knowledge of AMBA AXI/AHB/APB protocols.
• Expertise in test plan creation, testbench architecture, and test scenario development, including functional coverage and code coverage management.
• Strong analytical and problem-solving skills, with a proven ability to work independently.
• Excellent written and verbal communication and documentation skills.

Travel Time:

0% - 25%

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