Staff Digital Design Engineer, HBM

Req ID:

JR104396 Staff Digital Design Engineer, HBM

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Micron’s HIG HBM Digital Design Group is seeking a Digital Design Engineer to contribute to the architecture, RTL development, verification, and delivery of high‑performance digital logic blocks for advanced HBM memory products.

In this role, you will translate specifications into robust Verilog/SystemVerilog RTL, evaluate design tradeoffs across power, performance, and area, and apply strong fundamentals in digital logic, computer architecture, and low‑power methodologies. You will collaborate closely with verification, physical design, DFT, CAD, and system architecture teams to deliver high‑quality well‑documented digital designs. Success in this role requires strong technical communication skills, a proactive approach, and the ability to excel in a fast‑paced, highly collaborative engineering environment.

Responsibilities:

• Drive all stages of the digital design flow, including concept definition, specification, RTL implementation, verification support, documentation, and post‑silicon debug.

• Develop high‑quality RTL in Verilog/SystemVerilog using scalable, parameterized design techniques aligned to architectural specifications.

• Define and refine micro‑architecture for digital logic blocks, including FSMs, datapath, FIFOs, pipelines, and arbitration logic.

• Analyze tradeoffs across area, power, latency, and throughput, providing clear documentation and communication of design decisions.

• Perform CDC/RDC analysis, apply sound clocking and reset strategies, and identify early timing challenges.

• Support synthesis and static timing analysis by crafting and debugging SDC constraints, and interpreting timing reports.

• Apply low‑power design methodologies including CPF/UPF, clock gating, multi‑domain partitioning, and isolation/level shifter strategies.

• Collaborate with verification, DFT, physical design, and CAD teams to ensure robust design closure and high coverage, including scan/ATPG readiness and functional/formal verification support.

Minimum Qualifications:

• Bachelor’s degree or equivalent experience in Electrical Engineering with strong understanding of computer architecture (3–5 years proven experience).

• Sophisticated RTL design proficiency using Verilog/SystemVerilog with experience translating specifications into maintainable micro‑architecture and RTL.

• Solid grasp of digital logic fundamentals including FSMs, pipelines, datapath/control partitioning, and buffering/flow control structures.

• Experience with synthesis, STA, investigating CDC/RDC issues, and creating timing constraints.

• Proficiency in Linux environments with scripting skills (Python and/or Perl) to automate design flows and improve productivity.

Preferred Qualifications:

• Master’s degree in Electrical/Computer Engineering with 5–10 years of related experience.

• Knowledge of memory system concepts (DRAM/SRAM/

eFuse (electrical fuse), ECC/CRC techniques, DFT methodologies including memory/logic BIST and Using AI.

• Experience with AMBA/AXI/APB or comparable bus protocols, and working with custom or third‑party macros using behavioral and timing models.

Job Profile(s):

Semiconductor Design Engineer 3 - Semiconductor Design Engineer 4

Relocation Level: TBD

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