Principal Analog Design Engineer, HBM

Req ID:

JR93209 Principal Analog Design Engineer, HBM

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

We are seeking a Principal Analog Design Engineer to lead the design, integration, and delivery of advanced analog and mixed-signal IPs for High Bandwidth Memory (HBM) products. This role is critical in developing and integrating high-performance analog subsystems within the HBM logic die, enabling industry-leading bandwidth, power efficiency, and reliability.

As a principal engineer, you will provide deep technical leadership across analog design, IP integration, system alignment, and silicon execution, driving end-to-end success of HBM solutions.

Responsibilities will include, but are not limited to:

• Lead the design and own critical HBM analog circuits, including:

• High‑speed transmitters and receivers

• Clock generation and distribution (PLLs, DLLs, CDRs)

• SerDes‑related analog blocks

• Biasing, reference, and calibration circuits

• Power delivery and regulation circuits (LDOs, regulators)

• Define and lead IP interfaces, power domains, clocking schemes, and reset strategies across subsystems

• Perform detailed pre‑layout and post‑layout simulations

• Conduct PVT, Monte Carlo, mismatch, and aging analyses

• Work closely with layout engineers to define floorplanning and symmetry requirements, ensure matching, shielding, and EM/IR compliance

• Review and sign off on analog layouts

• Drive layout‑aware build optimizations for advanced nodes

• Define guidelines for analog build, documentation, and reuse

• Collaborate across analog, digital, system, packaging, and test teams

Minimum Qualifications:

• MS or PhD in Electrical Engineering or related field

• ~10–15+ years of experience in analog/mixed-signal IC build

Proven expertise in:

• High-speed interface design

• Clocking circuits (PLL/DLL/CDR)

• Power management circuits

• Strong experience in:

• Analog IP integration at subsystem or SoC level

• SPICE simulation, extraction, and modeling

• Silicon bring-up and lab validation

• Deep understanding of:

• Advanced CMOS processes

• Noise, jitter, SI/PI, and cross-domain coupling effects

Preferred Qualifications:

• Deep knowledge of DRAM sub‑system architecture, specification, operation, or build.

• Understanding of Physical Layout & Circuit Floor Planning

• Excellent Problem‑Solving & Analytical Skills

Job Profile(s):

Semiconductor Design Engineer 5

Relocation Level: TBD

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