Part-Time Lecturer for NM6604 Laboratory 1: Semiconductor Process and Device Simulation and for Part 1 of NM6605 Laboratory 2: Design and Modelling of Nanodevices (EEE)

The School of Electrical and Electronic Engineering (EEE) at Nanyang Technological University (NTU), Singapore, invites qualified candidates to apply as Part-Time Lecturer for two courses: NM6604 Laboratory 1: Semiconductor Process and Device Simulation and for Part 1 of NM6605 Laboratory 2: Design and Modelling of Nanodevices courses which will be offered to students taking the NTU-TUM M.Sc. Green Electronics Programme. The Part-Time Lecturer is expected to teach these postgraduate courses commencing in August 2026. The contents of each course is detailed below.

The objective of the 2-week NM6604 course is to impart to students the knowledge relevant to the fabrication and operation characteristics of modern semiconductor devices with hands-on practical sessions of TCAD simulations using the software VisualFab. Virtual Wafer Fabrication (VWF) simulations will first provide in-depth coverage of process simulation, followed by simulating a given CMOS process recipe and study profiles and layer structures. The students will have to simulate the DC characteristics of the “fabricated” device (MOS transistor) and analyze device operation with respect to potential, field, and carrier distributions as well as extract necessary I–V characteristics. Next, device-target vs. process-variable relations will have to be deduced. For this purpose, the students will have to devise wafer-split experiments using a Design of Experiments (DOE) approach, which will enable them to reveal the influence of process variations on transistor performance parameters.

NM6605 is also a 2-week course consisting of 2 parts. This advert relates only to Part I of this course, which is a direct and immediate continuation of the previous course NM6604. Specifically, Part I of NM6605 refers to MOSFET analytical equations, short-channel effects, compact model for circuit simulation, parameter extraction, and transistor optimization. Another DOE will be carried out and -based on it- the students will need to do another set of detailed simulations using the same software (VisualFab) as in NM6604. However, now the aim is to understand the effects of the scaling characteristics (gradual reduction of MOS gate length to sub-micron levels) on the transistor performance of the given technology.

Part II includes semiconductor fundamental, simulation of Si, Ge, and Sn band structures, quantum wells (QWs), energy sub-bands and wave functions, the k-p method. It also covers QW band structure and other quantum mechanics and solid-state physics aspects relevant for modern nanodevices.

The successful candidate should have extensive relevant industry experience and/or at least a PhD degree in Electrical & Electronic Engineering and a passion for teaching.

Further information about the School can be viewed at the following website:

EEE : https://www.ntu.edu.sg/eee/home

The successful candidate is expected to assume duty in August 2026 and is able to commit at least 5 months (1 semester) to this position.

Hiring Institution: NTU