- Location
- Hyderabad, TS,IN, IN
- Type
- Full-time
- Department
- IT
- Seniority
- Senior
- Education
- PhD
- Source
- Eightfold
Description
Experience: 12+ years in Pre-Silicon Verification (experience with DDR/GDDR/LPDDRmemory/SerDes PHY IP Verification is preferred) Expert-level proficiency in SystemVerilog, UVM, and advanced verification methodologies. Strong experience in Formal Verification tools and techniques. Solid understanding of SoC architecture, bus protocols (AXI, PCIe, etc.), and low-power build. Familiarity with AMS Co-Simulation and mixed-signal verification flows (preferred). Hands-on experience with simulation, coverage analysis, and regression management. Excellent problem-solving, debugging, and analytical skills. Proven ability to lead verification teams and influence technical direction. Bachelor's/Master's or PhD degree or equivalent experience in Electrical Engineering, Computer Engineering, or a related field. Exposure to Python/TCL scripting for automation. Define and drive verification architecture and methodology for next generation HBM designs. Develop verification plans, coverage strategies, and sign-off criteria. Architect and implement UVM-based testbenches and reusable verification components. Apply Formal Verification techniques for critical Collaborate strictly with build teams to ensure verification completeness and quality. Mentor and guide verification engineers on guidelines and advanced methodologies. Evaluate and integrate AMS Co-Simulation techniques for mixed-signal IP verification. Work closely with EDA vendors to adopt the latest tools and flows.