Director, Design For Test

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

As a Director of Design For Test at Marvell, you will lead a high-impact DFT organization responsible for DFT architecture, methodology, and execution across multiple advanced ASIC/SoC programs. Operating within Marvell's Custom Silicon Engineering team — a leader in multi-die designs for custom AI, XPU, and high-performance compute — you will manage team/teams of senior technical leads to deliver world-class test solutions for industry-first silicon challenges.

What You Can Expect

• Lead and manage a DFT organization of DFT engineers and engineering managers across programs and sites, accountable for headcount planning, hiring, performance, and talent development.
• Own DFT architecture definition and methodology governance for multiple concurrent custom ASIC/SoC programs at advanced process nodes (3nm, 2nm).
• Drive the DFT methodology roadmap — including scan, MBIST, IJTAG, ATPG, compression, OCC, and IP-DFT — ensuring alignment with design, PD, and product engineering teams.
• Partner with executive leadership and BU program management to define DFT resource plans, prioritize programs, and track delivery milestones.
• Serve as Marvell's primary DFT interface with key customers, presenting architecture proposals and managing technical risk in DFT for custom silicon engagements.
• Define and drive DFT automation and infrastructure improvements through the M1DPx/Tessent-based flow ecosystem to improve scale and quality.
• Establish and monitor DFT quality KPIs: test coverage, DPPM, test time, debug efficiency, and MPR readiness across the portfolio.
• Mentor and grow Director/Senior Manager, Staff, and Principal Engineer-level talent; act as a technical and cultural role model.
• Represent DFT in cross-functional design reviews, foundry engagements, and EDA vendor partnerships.
• Collaborate with product engineering and test operations to ensure smooth DFT handoff and post-silicon support.

What We're Looking For

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or related field with 15+ years of experience; 8+ years in DFT with 3+ years in people management.
• Proven experience managing DFT teams of 10+ engineers across distributed global sites.
• Strong DFT execution background: Scan, MBIST/BIRA/BISR, JTAG/IJTAG, ATPG (SAF/TDF), OCC, IP-DFX, post-silicon bring-up and debug on complex SoC designs.
• Demonstrated experience owning DFT architecture for at least 2–3 major tape-out programs at advanced nodes (7nm or below).
• Hands-on familiarity with Siemens Tessent DFT insertion flows.
• Proven ability to manage DFT execution risk, prioritize competing demands, and communicate program status to executive stakeholders.
• Strong cross-functional collaboration skills with Physical Design, STA, product engineering, and test operations teams.
• Experience with M1DPx or similar RTL/gate-level DFT flows is a strong plus.
• Excellent communication and leadership skills; demonstrated ability to build and sustain high-performing technical teams.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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