Mixed Signal SVE Engineer

Lead bring-up, debugging, and optimization of DDR/SerDes PHYs across post-silicon teams. Proactively identify and resolve issues to ensure successful product launches. Provide post-release support for PHY-related customer issues. Develop firmware and execute regression testing. Generate clear and detailed test reports and documentation. Hands-on experience with DDR/SerDes test development, debugging, and characterization. Proficiency in firmware development and scripting (Python preferred). Solid understanding of JEDEC and other electrical/protocol specifications. Strong grasp of PHY circuitry fundamentals (DLLs, I/O, calibration). Familiarity with signal integrity and probing techniques for memory buses. Skilled in using lab instruments (oscilloscopes, spectrum analyzers, logic analyzers, etc.). Detail-oriented with a focus on quality and ownership of deliverables. Excellent communication skills—both verbal and written. Experience with hands-on lab work, including soldering and system instrumentation. Experience applying machine learning or data science techniques to hardware validation or silicon debug. Knowledge of statistical modeling and data visualization for large-scale silicon test datasets. Ability to build and maintain automated pipelines for data collection, labeling, and model training. Understanding how AI can be used to enhance lab instrumentation workflows and regression analysis. Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.