Senior Engineer I - ASIC Verification

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Job Description:

Role Overview

You will be responsible for verifying DDR4/5 memory controllers and AXI input interfaces for IP-level designs, ensuring full protocol compliance, error handling, data integrity and performance computation for high-speed DDR interfaces.

Key Responsibilities

• Develop and maintain SystemVerilog UVM-based verification environments for DDR4/DDR5 memory controller and PHY IP.
• Define verification plans, design testbenches, and create directed and constrained-random testcases.
• Write and debug testcases and sequences for DDR protocol features (read/write operations, refresh, training, power-down modes).
• Validate ECC, parity, and command/address/data integrity mechanisms.
• Develop and debug scoreboards, assertions (SVA), and checkers for data integrity and protocol correctness.
• Integrate AXI, APB VIPs with DDR subsystem.
• Perform coverage analysis (code, functional, assertion) to ensure verification completeness.
• Debug RTL and simulation failures using waveform analysis (SimVision, Verdi).
• Work with design teams to debug RTL and root-cause functional/timing issues in RTL and GLS.  
• Collaborate with post-silicon and firmware teams for memory bring-up and validation.
• Mentor verification engineers and drive best practices
   

Technical Skills

• Strong knowledge of DDR protocol (JEDEC specifications).
• Experience with SystemVerilog, UVM, and verification methodology.
• Hands-on with simulation tools like Synopsys VCS, Cadence Xcelium, or Mentor Questa.
• Good understanding of memory controller architecture and timing parameters (setup/hold, tRCD, tRP, etc.).
• Knowledge of AXI protocol and its integration with DDR controller.
• Familiarity with assertions (SVA), scoreboarding, and functional coverage. Familiarity with GLS is a plus.
• Drive debug efficiency improvements by leveraging modern methodologies, script automation (Python), and integrating AI/LLM-assisted workflows to accelerate root-cause analysis and triage.

Soft Skills

• Strong analytical and debugging skills.
• Able to deliver tasks independently.
• Good communication and leadership skills.
• Comfortable collaborating across design, validation, and firmware teams.

Requirements/Qualifications:

B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or Computer Engineering.

10+ years of experience in SoC or IP-level verification (memory subsystems preferred)

Travel Time:

0% - 25%

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