Regional Graduate Program - Engineer Verification and Validation

We are searching for a talented individual with a good understanding of analog circuit design to drive the analog behavioral modeling role and to become an integral part of the Infineon R&D team. The successful candidate will join a dynamic team of designers, chip architects, and systems engineers to develop leading-edge high-performance power management solutions for the computing market. Education: BSEE, BSME, or equivalent with 1+ years of relevant verification experience Tools: Proficient with Cadence Virtuoso, ADE Explorer, Xcelium, and Spectre simulation flows Modeling: Experienced in Verilog-AMS/SystemVerilog and AMS behavioral modeling practices Scripting: Comfortable scripting in Python, and/or C/C++ for automation and data parsing Environment: Familiar with Unix/Linux command line, editors, and version control systems Soft Skills: Strong debugging skills, effective cross-functional communication, and ability to work independently and in teams Processes: Experience using bug tracking systems and maintaining reproducible simulation regressions Mobility: Willingness to travel ~20% for the RGP role for a two year period, then return to either Andover MA, Raleigh NC, or Austin TX at the end of the program We are on a journey to create the best Infineon for everyone. We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. Our hiring decisions are based on skills and experience. Even if you don't meet every requirement, we encourage you to apply. Please let your recruiter know if you need any accommodations during the interview process. Learn more about our various contact channels and about Diversity & Inclusion at Infineon. Methodology: Develop new strategies that leverage AI to aid in the improvement of the verification flow and translates to faster iteration cycles, better coverage testing, higher quality documentation, and overall product successes Modeling: Generate Verilog-AMS and SystemVerilog behavioral models and correlate results with schematic-level performance using targeted testbenches Testbench: Develop mixed-signal simulation workbenches in Cadence ADE Explorer and Xcelium and automate regression runs Schematic/Netlist: Create schematics, produce schematic netlists for simulation, and maintain hierarchy configurations for tool flows Verification: Verify device-level and system-level requirements through simulation, interpreting results and documenting discrepancies DFT/Testability: Contribute to verification of DFT plans, digital scan support, ATE preparation, and bench testability assessments Debugging: Debug analog and digital integration issues and drive resolution with design and test teams Collaboration: Coordinate with design, test, and production teams to support pre-silicon verification and production IC validation Rotation travel: Participate in training rotations across 2-4 divisions, work with multiple managers, and travel to various U.S. locations as needed for a two year period Presentations: Create and present progress PowerPoint updates for the program, product demonstrations (if applicable) for internal and external teams as needed Mentoring: Mentor future RGP members during your last year as a RGP (roughly 1 hour per month during active mentoring periods)