- Location
- Mumbai, IN
- Type
- Full-time
- Seniority
- Lead
- Source
- Breezy HR
Description
Company- iRage Capital - ( https://irage.in/ )
Role Type- Full Time
Location- Mumbai
Position Name -FPGA Lead
About Us
iRage is one of India's leading high-frequency trading firms. We build and own everything
in-house, from ultra-low-latency execution to our entire trading infrastructure. Our systems
deliver some of the lowest latencies in the market, with order-send speeds under 100
nanoseconds - but the harder problem we've solved is keeping that latency low at scale. We
run thousands of independent portfolios in parallel, carrying overnight positions across
thousands of instruments, with tooling that coordinates state and information across
hundreds of servers spanning multiple data centres in real time.
The stack is ours end to end: custom FPGA pipelines - including PHY and MAC layers we built
on hardware firmware in-house - and a C++ codebase we control from market-data
ingestion through order entry and risk. We run experiments over days just to shave off a
single clock cycle.
But great technology alone doesn't move markets. Our quant and tech teams work side by
side, and the results speak for themselves: millions of trades a day. To put that in perspective,
we handle the equivalent of several Big Billion Days in a single day, every day, at lightning
speed. iRage is where deep technical expertise meets real market impact, in one of the
world's fastest-growing trading ecosystems.
Role Summary - FPGA Lead
As the FPGA Lead you'll own the greenfield implementation: architecting and building the RTL
that moves market data and orders in nanoseconds, setting the design and verification
standards the team will work to, and deciding where to lean on existing IP versus building
from scratch. This is a hands-on role where design choices translate directly into trading
edge.
What you'll do
● Own the FPGA architecture for latency-critical trading paths (market data ingest, order
entry, host interface).
● Write and optimize production RTL, then drive it to timing closure on the latest
AMD/Xilinx devices.
● Set RTL, verification, and resource-management standards for a growing FPGA team.
● Make build-vs-buy decisions on IP, and integrate or replace existing cores as needed.
● Work directly with trading, quant, and infra teams to turn latency requirements into
hardware.
Must have
● 7+ years in FPGA development, with deep hands-on RTL in Verilog/SystemVerilog.
● Demonstrated ownership of shipped designs (written from scratch, not just
maintained) in at least two of: network packet processing (PCS, MAC, UDP, TCP/IP),
high-speed Ethernet, PCI Express, memory interfaces.
● Proven timing closure on complex designs, plus strong resource management and
latency optimization.
● Fluency with simulation and toolchains: Vivado, Vitis, ModelSim/Questa or Xilinx
simulator.
● Solid modern C and Python for tooling, host-side integration, and automation.
Nice to have
● Experience on current-gen Xilinx architectures (UltraScale+, Versal).
● Cryptographic cores / accelerators.
● Low-latency networking or trading-systems background.
Here’s what we offer:
● Compensation – competitive package, plus a meaningful performance bonus
● Generous paid time off – Recharge & come back sharper.
● Work with the best – Collaborate with top-tier global talent.
● Adventure together – Annual offsites (international & domestic) plus regular team
outings.
● Performance rewards – Attractive bonuses for those who go above & beyond.
● Health covered – Comprehensive insurance so you’re always protected.
● Fun, not just work – On-site sports, games, & a lively workspace.
● Learn & lead – Regular knowledge-sharing sessions led by your peers.
● Annual Education Allowance – Take any external course, or certification that makes
you better at your craft.
● Stay fit – Gym memberships with equal employer contribution to keep you at your
best.
● Relocation support – Smooth move? We’ve got your back.
● Friendly competition – Work challenges & extracurricular contests to keep things exciting