- Location
- Palo Alto, CA · Austin, TX · Vancouver, BC · Remote
- Workplace
- Remote
- Type
- Full-time
- Department
- Software
- Experience
- 3+ years
- Source
- Lever
Description
About us
Mythic is building the future of AI computing with breakthrough analog technology that delivers 100× the performance of traditional digital systems at the same power and cost. This unlocks bigger, more capable models and faster, more responsive applications—whether in edge devices like drones, robotics, and sensors, or in cloud and data center environments. Our technology powers everything from large language models and CNNs to advanced signal processing, and is engineered to operate from –40 °C to +125 °C, making it ideal for industrial, automotive, aerospace, and defense.
We’ve raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets.
About the role
Help push the boundaries of what can run on our accelerator. You’ll design compiler IRs and lowering strategies to support algorithmic workloads with irregular or dynamic control flow—loops, branches, and iterative methods—going beyond static neural networks. Working side by side with hardware engineers, you’ll influence ISA and execution model co-design to unlock new algorithm classes on analog and digital subsystems. The result: a compiler that makes complex algorithms practical to deploy while staying seamless for developers.
Skills
PythonC++PyTorchPrototyping
Benefits
The opportunity to make algorithmic and control-flow-heavy workloads practical on novel accelerator hardware.A role that bridges compiler design and hardware co-design, shaping both the IR and the accelerator architecture.A collaborative, innovative team that values engineering rigor, continuous integration, and user-focused design.Competitive compensation, equity, and benefits package.
