- Salary
- $160k – $200k
- Location
- San Jose, California, United States · California
- Department
- ASIC Engineering
- Experience
- 5+ years
- Education
- Master
- Source
- Greenhouse
Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
About the Role
As a Physical Design & CAD Engineer, you will serve as a Technical Lead developing Astera Labs’ next-generation connectivity ASICs for cloud and AI infrastructure.
This role combines Physical Design CAD methodology development with hands-on place-and-route (PNR) implementation. You will develop and optimize automated design flows for advanced process nodes while contributing to block-level physical design, timing closure, and GDSII signoff.
You will collaborate with cross-functional engineering teams to improve design efficiency, automation, and silicon implementation.
What You'll Do
- Develop and maintain Physical Design CAD flows and methodologies for advanced process nodes.
- Build automation frameworks using Python and Tcl to support synthesis through signoff.
- Perform hands-on Physical Design and PNR, including floorplanning, placement, CTS, routing, and timing closure.
- Develop and optimize EDA tool flows for timing analysis, extraction, EM/IR, and physical verification.
- Support block-level implementation from synthesis through GDSII signoff.
- Improve design quality, automation, and flow efficiency.
- Collaborate with design, verification, and engineering teams to support ASIC development and tapeout.
Basic Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's degree preferred.
- 5+ years of experience in ASIC Physical Design, CAD methodology, or design automation.
- Strong understanding of physical design implementation and RTL-to-GDSII methodologies.
- Experience developing or maintaining Physical Design CAD flows.
- Hands-on experience with PNR, timing closure, and physical design signoff.
- Proficiency in Python and/or Tcl scripting.
- Experience with Cadence and/or Synopsys physical design tools.
- Experience with advanced semiconductor process nodes (7nm or below).
Preferred Qualifications
- Experience with 3nm or more advanced process technologies.
- Experience building automated CAD flows from synthesis through signoff.
- Familiarity with Cadence Innovus, Tempus, Genus, Synopsys ICC2, Fusion Compiler, and PrimeTime.
- Experience with EM/IR analysis, DRC/LVS, ECO, and timing signoff methodologies.
- Experience with block-level ownership through tapeout.
- Experience developing scalable CAD methodologies and automation frameworks.
Compensation
The base salary range for this role is $160,000–$200,000 USD. Your salary will be determined based on your experience and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.