- Location
- Bay Area
- Workplace
- Onsite
- Type
- Full-time
- Department
- Engineering
- Seniority
- Senior
- Source
- Lever
Description
ABOUT THE ROLE
As a Sr Staff / Principal Physical Verification Engineer, you will be the technical owner of all signoff physical verification activities across advanced process nodes. You will lead DRC, LVS, and DFM sign-off at chip top level, drive hierarchical verification strategies, and own bump planning and package-level DRC across Intel, TSMC, Samsung, and GlobalFoundries technologies spanning 28nm through 2nm. You will be a partner with physical design, package engineering, and foundry teams to ensure first-pass tape out success on chiplet-based products.
Skills
PythonPerlCompliance
