- Location
- San Diego, CA,US, US · Santa Clara, CA,US, US
- Type
- Full-time
- Department
- Engineering
- Experience
- 6+ years
- Education
- PhD
- Source
- Eightfold
Description
Bachelor's degree in electrical engineering, or related Sciences 6+ years of experience in ASIC design Experience and understanding of ASIC design flow: Architecture, Microarchitecture, verilog/system-verilog RTL design, Clock Domain Crossings, DFT, synthesis, and timing closure Knowledge of bus protocols, clocks/resets, debug concepts Problem solving, strong communication and teamwork skills Self-driven, motivated, able to work with minimum supervision Experience with microcontroller CPUs, Busses (AHB/AXI/others), or Peripherals Experience with system level architecture, complex subsystems, integration of analog and digital IP, implementation techniques, silicon test Experience with High-speed, Low Area, and Low Power architecture Experience in hardware security fields like Root of Trust, RNG, symmetric and asymmetric crypto, side-channel, error correction codes, hardening, etc Experience in verification, modeling, test-planning Bachelor's degree minimum, Master's or PhD preferred. Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.