- Location
- Austin, Texas, United States
- Workplace
- Onsite
- Type
- full-time
- Department
- HW Platform Dev.
- Seniority
- Senior
- Education
- Master
- Industry
- Technology
- Category
- Engineering
- Role type
- Individual Contributor
- Environment
- Office
- Source
- Greenhouse
Overview
As a Senior Signal Integrity Engineer, you'll develop, validate, and optimize high-speed signaling solutions across blade- and rack-level architectures for advanced compute platforms. Your work will span silicon, package, interconnect, board, and system design with emphasis on measurement, simulation correlation, and technical communication. Responsibilities include end-to-end SI analysis, optimizing high-speed interfaces (PCIe Gen4/5/6, Ethernet, DDR, SerDes), performing time/frequency domain simulations using tools like Ansys HFSS and Keysight ADS, lab validation with VNA/TDR/BERT, correlating simulations with measurements, and collaborating with cross-functional teams. Requirements include Bachelor's or Master's in Electrical/Computer Engineering, strong SI experience, hands-on measurement expertise, knowledge of high-speed interfaces, and proficiency with SI/PI simulation tools. Preferred qualifications include data center experience, blade/backplane architecture knowledge, thermal/mechanical considerations, and scripting language experience.
Description
About the Role
We are seeking a Senior Signal Integrity Engineer to develop, validate, and optimize high-speed signaling solutions across blade- and rack-level architectures for advanced compute platforms. This role sits at the intersection of silicon, package, interconnect, board, and system design, with a strong emphasis on hands-on measurement, simulation correlation, and cross-functional technical communication.
Key Responsibilities
- End-to-end signal integrity analysis for blade- and rack-level system architectures.
- Analyze and optimize high-speed and low-speed I/O interfaces, including PCIe Gen4/5/6, Ethernet, DDR, SerDes, SPI, I2C, etc. and related interconnects.
- Perform time-domain and frequency-domain simulations using tools such as Ansys HFSS, Keysight ADS, Cadence Sigrity, CST, SPICE, or similar.
- Support hands-on lab validation using VNA, TDR, BERT, and high-speed oscilloscopes.
- Correlate simulation results with lab measurements to identify margin gaps, debug issues, and improve design methodology.
- Collaborate with silicon, package, board, connector, cable, and system design teams to optimize I/O channel performance.
- Work with interconnect vendors and ODMs to guide board layout, stack-ups, routing rules, and system design decisions.
- Review schematics, layouts, simulation results, and validation data for blade, backplane, and rack-level hardware.
- Prepare and communicate clear validation reports, measurement summaries, debug findings, and technical recommendations to internal teams, vendors, and senior technical stakeholders.
Required Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Strong experience in signal integrity for high-speed digital systems.
- Hands-on measurement expertise using VNAs, TDRs, BERTs, and high-speed oscilloscopes.
- Experience measuring and analyzing S-parameters, impedance profiles, eye diagrams, jitter, timing margins, insertion loss, return loss, and crosstalk.
- Knowledge of high-speed interfaces such as PCIe Gen4/5/6, Ethernet, DDR, SerDes, and related I/O technologies.
- Experience with SI/PI simulation tools such as HFSS, ADS, Sigrity, CST, SPICE, or equivalent.
- Ability to correlate lab measurements with simulations and use data to guide design decisions.
- Strong communication skills, including the ability to produce clear validation reports, present technical findings, and work effectively across multi-functional engineering teams.
Preferred Qualifications
- Experience in hyperscale, data center, cloud infrastructure, or advanced compute hardware environments.
- Experience with blade, backplane, board-to-board, cable, or rack-level interconnect architectures.
- Knowledge of thermal and mechanical considerations that impact SI/PI performance.
- Experience with calibration, de-embedding, fixture design, lab automation, or measurement methodology development.
- Experience using Python, MATLAB, or similar scripting languages for simulation automation, measurement automation, and data analysis.
Tools / Technologies
Measurement: VNA, TDR, BERT, high-speed oscilloscopes
Simulation: Ansys HFSS, Keysight ADS, Cadence Sigrity, CST, SPICE
Interfaces: PCIe Gen4/5/6, Ethernet, DDR, SerDes, SPI, high-speed interconnects
Analysis: S-parameters, eye diagrams, jitter, timing margins, impedance control, crosstalk, insertion loss, return loss, de-embedding, measurement-to-simulation correlation
Why Join Us
This is an opportunity to work on complex, high-performance compute platforms while partnering with experienced technical leaders, ODMs, and interconnect vendors. You will play a key role in defining, measuring, validating, and optimizing next-generation system-level I/O performance.
USA Benefits
In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
