- Location
- Riga, Latvia · AST - Latvia
- Department
- IT
- Seniority
- Senior
- Education
- Master
Description
AST SpaceMobile is building the first and only global cellular broadband network in space to operate directly with standard, unmodified mobile devices based on our extensive IP and patent portfolio and designed for both commercial and government applications. Our engineers and space scientists are on a mission to eliminate the connectivity gaps faced by today’s five billion mobile subscribers and finally bring broadband to the billions who remain unconnected.
Position Overview
We are seeking a Senior FPGA Team Lead with deep expertise in signal processing and high-speed digital interfaces. The role requires a highly experienced engineer capable of leading complex FPGA developments, making architectural decisions, and guiding a multidisciplinary team.
Key Responsibilities
- Lead architecture, design, and implementation of complex FPGA-based systems.
- Provide technical leadership and mentorship to FPGA engineers.
- Drive system-level design decisions in collaboration with system, RF, hardware, and software teams.
- Design and implement advanced DSP algorithms (filtering, channelization, etc.).
- Develop and integrate high-speed data paths and interfaces.
- Ensure signal integrity and robust operation of high-speed links.
- Optimize designs for performance, latency, and resource utilization.
- Own the full development lifecycle: requirements → design → simulation → implementation → validation.
- Lead lab bring-up, debugging, and performance optimization.
- Define best practices, coding standards, and design methodologies.
Qualifications
Education
- B.Sc. or M.Sc. in Electrical Engineering or related field.
Experience
- A minimum of 8 years of FPGA design experience.
- Strong hands-on experience in FPGA design and development.
- Strong expertise in digital signal processing (DSP).
- High proficiency in VHDL / Verilog / SystemVerilog.
- Strong system-level understanding and integration experience.
- Deep understanding of SERDES, transceivers, and clocking architectures.
- Proven experience with high-speed link bring-up and lab debugging.
- Fluent English (spoken and written).
Preferred Qualifications
- Experience with Xilinx / AMD FPGA devices and toolchains (Vivado, Vitis).
- Experience with RF / wireless communication systems (LTE/5G).
- Experience with RFSoC / Zynq platforms.
- MATLAB / Python for algorithm development.
- Experience with real-time, high-throughput systems.
Soft Skills
- Strong leadership and mentoring capabilities.
- Ability to drive complex technical decisions independently.
- Excellent analytical and problem-solving skills.
- Strong communication and cross-functional collaboration.
Technology Stack
- VHDL.
- Verilog.
- SystemVerilog.
- Xilinx / AMD FPGA devices.
- Vivado.
- Vitis.
- MATLAB.
- Python.
- RFSoC.
- Zynq.
Physical Requirements
- Ability to work in a standard office environment and use a computer for extended periods.
This job description may not be inclusive to the duties and responsibilities listed. Additional tasks may be assigned to the employee from time to time or the scope of the job may change as needed by business demands.
AST SpaceMobile is an Equal Opportunity, at will Employer; employment is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
