Responsibilities:

  -Execute Scan insertion, Scan DRC check and debug. review DRC reports, debug and resolve DRCs

  -Tmax pattern generation, Optimize ATPG patterns and improve Fault coverage, check and debug ATPG DRCs

  -Knowledge of Codec/EDT architecture, debug scan issues indepedently/with minimum supervision

  -Verify ATPG tests in Zero delay and SDF annotated simulations

  -Debug simulation failures in VCS, Verdi and other simulators

Requirements:

   -B.Tech / M.Tech (preferred) with 1-3 years of experience in DFT

   -Strong knowledge of DFT architecture, methodologies and structural debug concepts:  JTAG, IEEE1500, Scan tests debug

   -Experience in executing DFT for multi multimillion gate multi clock domain SoCs

   -Hands on experience in SCAN, ATPG and JTAG implementation at block and chip level

   -Experience in using simulators and waveform debugging tools such as VCS and Verdi

   -Hands on experience in using Synopsys DFT tools like Testmax, Tetramax, DC & FC

   -Knowledge of Python, , Shell scripting, Makefiles, TCL

   -Excellent problem-solving skills and highly self-motivated.

Why Cisco? 

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you.