Design Verification Engineers (DV)

We are hiring Design verification Engineers PCIe Design IP R & D Team at Bangalore.Skills: Strong Experience in SV/UVM/Test bench development, working knowledge of PCIe / CXL ProtocolExperience : 5+ yrsNotice period: Immediate to 60 daysSalary : Best in Industry Key Responsibilities:Lead end to end IP verification activitiesDevelop detail test plans and verification strategiesBuild and maintain UVM based test benches using system verilogKnowledge of protocols (AXI/ AHB/APB) and PCIe is must