- Location
- Santa Clara, CA,US, US
- Type
- Full-time
- Department
- Engineering
- Seniority
- Senior
- Source
- Eightfold
Description
As an integral part of product engineering, you will drive our latest architecture designs to market. Design FT (final test) test processes to enhance manufacturing efficiency for our latest GPUs, built in leading-edge process technology. Identify and resolve yield bottlenecks, analyze and drive test failures, wafer & package level failures on Automatic Test Equipment (ATE). Propose DOEs and come up with solutions to complex characterization problems. Cross functionally lead efforts with design, foundry, DFT, test, Planning and quality to root-cause and solve technical problems. Have the opportunity to influence future ASIC designs to improve test coverage and enable better product yield, test time, silicon bring-up and releases. Experience with digital design, circuit analysis, characterization and qualification. Proficient in statistical data analysis using JMP software or other tools. Ability to define and drive problems to closure independently with minimal supervision. Experience with logic or SRAM and Voltage/Frequency characterization.