MTS - Analog Layout

Req. ID:

JR114958 MTS - Analog Layout

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Key Responsibilities

Technical Ownership

• Lead full‑custom layout for complex Analog / Mixed‑Signal IP blocks, including but not limited to:
• Bandgap references, LDOs and regulators, Charge pumps (positive/negative)
• PLLs, delay lines, oscillators, IO & PHY‑related analog blocks
• Temperature sensors, bias circuits
• ESD protection devices and clamps
• Own layout quality from floor‑planning to tape‑out, ensuring:
• Device matching and symmetry, noise isolation and substrate strategies
• Robust power/ground planning
• Yield, reliability, and DFM compliance
• Work closely with circuit designers to translate performance goals into layout strategies, especially in noise‑sensitive mixed‑signal environments.

Advanced Technology Expertise

• Strong experience in advanced FinFET nodes such as TSMC 3nm, 5nm, including:
• Fin quantization awareness
• Multi‑Vt, multi‑fin strategies
• Advanced metal stack planning
• Solid background in planar CMOS technologies (e.g., 40nm, 65nm, 90nm) for analog robustness and legacy IP support.
• Deep understanding of foundry PDKs, layout‑dependent effects (LDEs), and process variability.

Layout Verification & Signoff

• Drive and close DRC, LVS, ERC, ANTENNA, and reliability checks.
• Review and address issues related to:
• EM/IR, latch‑up, ESD window compliance
• Device stress and matching degradation
• Interface with foundry and CAD teams for waiver management and signoff convergence.

Leadership & Mentorship

• Provide technical guidance and design reviews for junior and mid‑level layout engineers.
• Establish and document best‑known methods (BKMs) for AMS layout across nodes.
• Drive IP reuse, layout template development, and methodology improvements.

AI usage proficiency

• Strong understanding of AI/ML and Generative AI concepts, with ability to identify high-value applications in circuit layout.
• Proficiency in Python/scripting and EDA automation to develop AI-assisted layout and verification solutions.
• Ability to translate layout expertise into constraints, algorithms, datasets, and measurable optimization objectives.
• Experience developing, integrating, and validating AI-driven methodologies against traditional designer-driven flows.

Job Profile(s):

Semiconductor Design Eng MTS

Relocation level: (TBD)

Before Getting Started

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As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.