CAD and PPA Methodology Engineer

Implementation and delivery of GPU cores from RTL to GDSII Semi-custom design flow and methodology development Identifying areas for flow and process improvements Verilog and System-Verilog languages RTL synthesis using physically aware tools Design constraint management for power, timing, clocking, interfaces Formal Verification for RTL-netlist and netlist-netlist checks Clock Tree Analysis and Optimization At-least 5-7 years of experience developing methodologies for PPA improvement Basic understanding of digital design and RTL development Hands on experience with EDA tools such as Synopsys Fusion Compiler, Synopsys RTL-Architect, PrimePower,PrimeTime and Prime Closure Script writing experience in UNIX shell, Python, Perl and/or TCL Excellent interpersonal and analytical skills as well as ability to work independently Highly motivated, excellent team spirit, obsession with deliverable quality and customer oriented Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 3+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. OR PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. Managing design goals and tradeoffs in power, performance, and area