Physical Design CAD Engineer

You will be in charge of developing physical design, synthesis, STA and Logic eq methodologies for implementation of networking chips and SOCs. Work closely with block owners. full Chip STA engineers and project managers to assure high quality and timely convergence. Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips. Additional responsibilities include participating and developing flow and tool methodologies for chip floorplan, power and clock distribution, P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects. Expertise in analysing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes. Experience in methodology definition / flow owner of synthesis / Place and Route/ STA steps is an advantage.