DRAM PHY Designer, up to Staff

Architect, design, and implement high-speed PHY circuits Create layouts that optimize circuit placement, signal routing, and power delivery Develop robust power delivery to the PHY design Simulate signal integrity and SNR performance together with the package and board s-parameter model Simulate pre-layout and post-layout mixed-mode circuits under PVT corners Incorporate power management features to reduce energy consumption Use state-of-the-art design and simulation tools to simulate the circuit behavior and manufacturability readiness Develop behavioral, timing, and power models of the circuits to guide the architecture choices across AI, compute, and mobile workloads Floorplan PHY circuits under manufacturing constraints, testability, repairability, and high performance Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products. Creates advanced architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements. Collaborates across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs. Evaluates all aspects of complex process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow. Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable advanced architecture and design of multiple complex blocks/SoC or IC Packages. Writes and reviews detailed technical documentation for complex EDA/IP/ASIC projects. Works independently with minimal supervision. Knowledge of timing circuits such as DLL, PLL Knowledge of analog building blocks Knowledge of SERDES, phase and duty cycle adjustment circuits Knowledge of LPDDR, HBM, and IO interfaces Knowledge of eye diagram and noise sources Master's or Ph.D. in Electrical Engineering and a related field Familiar with package design Experience in scripting language (Perl/Python) Familiar with the DRAM datasheets and IO interfaces Self-Starter with good communication skills and team-working spirit Strong problem-solving and analytical skills Ability to work independently and as part of a team Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science. 6+ years of ASIC design, verification, validation, integration, or related work experience. 2+ years of experience with architecture and design tools. 2+ years of experience with scripting tools and programming languages. 2+ years of experience with design verification methods. 1+ year of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).