Hiring.Camp

Processor ASIC RTL Design Engineer

Qualcomm

·

Jan 22, 2026

Location
San Diego, CA,US, US
Type
Full-time
Department
Engineering
Experience
2+ years
Education
PhD
Source
Eightfold

Description

Work with system architecture team to define micro-architecture documentation for various blocks in Hexagon/NPU and sub-system Develop RTL for multiple logic blocks of Hexagon/NPU and sub-system for SoC integration Run various frontend tools to check for linting, clock domain crossing, power intent etc Work with physical design team on design constraints and timing closure Work on area and power optimization Work with verification team to collaborate on test plan, test debug, coverage plan and coverage closure Support internal hardware integration Provide ideas and further the innovation of ASICs, IP cores, and process flows functional and structural RTL design in system Verilog, design partitioning, simulation and regression, collaboration with design verification team. Familiar with latest design tools (such as linting, CDC, LEC, CLP etc) Processor integration Bus interface Computer architecture Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 2+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 1+ year of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Science, Computer Engineering, or related field. 2+ years of experience with high-performance microprocessor design.

Skills

GoR.NETSalesforceiOS