- Type
- Full-time
- Source
- Eightfold
Description
## Join our Team
About this opportunity
Are you a university student looking for an opportunity to apply your studies to a challenging real-world research problem? Join Ericsson in Lund for a Master’s thesis exploring how artificial intelligence can support engineers in reducing power consumption at the RTL level.
What you will do
Power consumption is strongly influenced by RTL decisions related to switching activity, clocking, data movement, and memory access. You will investigate an AI-assisted, human-in-the-loop workflow that analyzes RTL, activity data, and power reports to identify power hotspots and suggest potential RTL optimizations. The work will focus on front-end and RTL power estimation.
- Learn about and help define representative use cases for RTL power estimation.
- Establish a baseline power-estimation flow with guidance from the thesis supervisors.
- Analyze switching, gate, and memory activity together with power reports.
- Explore how AI can identify power hotspots and propose RTL-level optimizations.
- Implement and validate selected alternatives through simulation, synthesis, and power estimation.
- Compare the results for dynamic power, area, timing, functional correctness, and engineering effort.
- Document your methodology, experiments, results, and conclusions clearly.
The skills you bring
- Knowledge in digital hardware design, computer architecture, electronics, embedded systems or a related field.
- Basic knowledge of Verilog or SystemVerilog; experience from university assignments or personal projects is welcome.
- Interest in artificial intelligence, machine learning, or AI-assisted engineering workflows.
- Eagerness to learn and explore new concepts.
- Ability to analyze data, communicate findings, and document work clearly.
- A structured and self-motivated approach to academic project work.
Skills
Machine Learning