Memory Yield Engineer, Staff

Yield Monitoring & Analysis Track fab in-line/WAT measurement data to ensure process stability and compliance with specifications. Perform statistical wafer/package-level test data analysis, applying memory repair schemes and correlating fab in-line/WAT data. Support failure analysis during SOC + memory system-level characterization and reliability qualification tests. Coordinate test flow/hardware setup and ensure smooth integration across teams. Support failure analysis for customer return samples. Minimum 7 years in DRAM test and wafer yield analysis and improvement engineering. Strong knowledge of DRAM test, processes, fab defect control, in-line/WAT/AC/DC measurement data analysis, and failure analysis. Experience in DRAM product qualification and repair schemes for yield improvement. Ability to define test coverage, fab process monitoring specs and wafer/package level test conditions for mature yield achievement. Familiarity with DRAM package-level test and yield improvement, memory process integration, basic device physics, design verification, and test patterns. DRAM product engineer experience Flash memory yield improvement experience. Broader knowledge in device physics, design, 3D wafer bonding, and test flow optimization to minimize memory fail in field. Min Bachelor's degree in Electrical Engineering (or equivalent engineering) required. Master's or PhD in Electrical Engineering preferred. Strong multitasking ability and proactive leadership in supplier engagement. Excellent written and verbal communication skills in English. Strong interpersonal skills for effective teamwork. Willingness to travel occasionally to supplier sites. Commitment to continuous learning in new memory engineering domains. Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.