Algorithm Engineer, Senior/Staff

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Company:

Qualcomm China

## Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Work on algorithm development, system modeling, and performance analysis for advanced communication and connectivity products. The candidate should have hands-on experience in system-level simulation of wired communication chips.

Qualifications

• Degree in Electrical Engineering, Communications Engineering, Computer Engineering, or a related field.
• Strong knowledge of digital signal processing and communication systems.
• Hands-on experience with LDPC coding and decoding algorithms.
• Proficiency in C++ and MATLAB.
• Basic understanding of analog signal processing and mixed-signal systems.
• Good analytical, problem-solving, and communication skills.

Preferred Qualifications

• Experience with Ethernet PHY, SerDes, or other high-speed wired communication systems.
• Experience with link-level or system-level modeling, including channel models, equalization, noise, and interference.
• Familiarity with FEC architectures, fixed-point implementation, or hardware-oriented algorithm development.

PRINCIPAL DUTIES AND RESPONSIBILITIES:

• Develop and evaluate LDPC decoding algorithms and related signal processing techniques.
• Build system-level simulation models using C++ and MATLAB.
• Analyze link performance, identify performance bottlenecks, and propose algorithm or architecture improvements.
• Work across digital and analog domains to understand system-level interactions and implementation trade-offs.
• Collaborate with architecture, digital design, analog, validation, and software teams.
• Support algorithm implementation, debugging, and performance optimization.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

OR

Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

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