Staff Engineer, ASIC IP STA

Req. ID:

JR111352 Staff Engineer, ASIC IP STA

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

### ASIC IP STA Engineer (6-10 Years) | DDR PHY / ONFI PHY / IO Expander

Location: Bengaluru, India

Experience: 6-10 Years

Enducational Qualification : BE/B-Tech/M-Tech (EEE, ECE, Micron Electronics, VLSI)

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Key Requirements

• Member of the AMS IP Physical Design team, responsible for post-layout STA signoff and timing closure of high-speed interface IPs, with close collaboration across IP Design, SoC Synthesis, and SoC Physical Design teams throughout IP development and SoC integration.
• 6-10 years of experience in Static Timing Analysis (STA) with a proven track record of 4+ successful tapeouts.
• Strong hands-on expertise with Cadence Tempus (preferred).
• In-depth experience in MMMC timing analysis and closure across functional, scan, MBIST, and other DFT modes.
• Experience working on high-speed Memory Interface IPs such as DDR PHY, ONFI PHY, IO Expander (IOE), or similar high-performance interface designs.
• Strong understanding of timing constraints development, validation, and debug, including clocks, generated clocks, timing exceptions, and mode-specific constraints.
• Experience in Liberty (.lib) and ETM timing model generation, validation, correlation, and quality assessment.
• Ability to deliver early timing models (.lib/ETM) and ensure high-quality timing collateral to enable smooth and predictable SoC integration.
• Hands-on experience with SDF generation, validation, and Gate-Level Simulation (GLS) support for verification teams.
• Solid understanding of setup/hold analysis, recovery/removal checks, pulse-width verification, OCV/AOCV/POCV methodologies, and SI-aware timing signoff.
• Experience with the Cadence digital implementation and signoff flow, including Genus, Innovus, and Tempus.
• Proficiency in TCL and/or Python for timing analysis, methodology development, and flow automation.
• Exposure to AI/ML-enabled EDA methodologies, leveraging AI-assisted workflows for timing analysis, timing closure, constraint validation, root-cause analysis, and productivity improvement.
• Strong analytical, debugging, communication, and stakeholder management skills, with the ability to drive timing closure across cross-functional teams.

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Preferred Qualifications

• Experience with advanced-node, high-frequency designs including LPDDR/DDR, ONFI, IO Expander, or similar memory and interface IPs.
• Exposure to AMS/Digital-on-Top IP development flows and timing signoff challenges associated with mixed-signal integrations.
• Familiarity with AI-powered EDA solutions, Agentic AI workflows for design automation and productivity enhancement.

Job Profile(s):

ASIC Engineer 4

Relocation level: (TBD)

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