- Location
- San Diego, CA,US, US
- Type
- Full-time
- Department
- Engineering
- Experience
- 2+ years
- Education
- PhD
- Source
- Eightfold
Description
1. Work in our MSIP analog design team to develop various mixed-signal IP above including architecture definition, and analog/digital design partitioning and schematic design. 2. Schematic capture and circuit simulations in the Cadence Virtuoso tool suite. 3. Work with cross functional teams (i.e. layout and digital teams) on design implementation, verification and IP delivery to SOC customers 4. Work with product test teams for post-silicon verification, bringup, debug, and production support Master's degree in Electrical Engineering or related field. Demostrated interrest in analog circuit design by course selections and/or work experience. Experience working with ASIC design tools such as Cadence Virtuoso. Several years of industry experience in the area of analog integrated circuit/system design. Experience as an analog designer of mixed-signal IPs, such as SerDes, DDR, PLL, DAC, ADC, sensors Familiar with Matlab and Python and good understanding of architecture, system and integration aspects for mixed-signal Good understanding of design for yield and production challenges Good understanding of Signals and Systems, Sampled Domain signal processing a plus Bachelor's Degree in Electrical Engineering with 2+ years of experience with analog or mixed-signal integrated circuit design in nanometer planar CMOS or FinFET and 2+ years of ASIC design, verification, or related work experience. OR Master's degree in Electrical Engineering or related field and 2+ years of ASIC design, verification, or related work experience. OR PhD in Electrical Engineering or related field. 2+ years of experience using one or more design tools (e.g., CADENCE, SPICE, MATLAB, and/or Verilog/VHDL).