- Location
- Bengaluru, KA,IN, IN
- Type
- Full-time
- Department
- Engineering
- Seniority
- Lead
- Source
- Eightfold
Description
Responsible for leading Physical Design and Timing Closure of lowpower SoCs targeted for IoT/MCU markets. - Responsible to achieve die area, performance, power goals forhierarchical blocks and top. Drive physical design implementation which includes package co-design,floorplanning, power grid design and signoff, place and route, timingclosure, physical verification checks. - Influence tools, flows and methodology activities to improve upon QoR. Interact with cross-functional team members to improve design,methodology and process aspects. Technical Expertise: - Deep and broad understanding of physical design and timing convergence of hierarchical SoCs Expert user of industry standard tools and flow/automation forphysical design and signoff In-depth knowledge of process technologies and associated physicaldesign challenges Deep understanding of low power design techniques and implementation methodologies IFX Behaviours: Ability to solve complex problems by proactively involving expert networks Drives technical decisions in area of expertise and takesresponsibility for implementation Coordinates with colleagues and actively shares expertise with others Facilitates and encourages innovation within own domain of expertise Cooperates across boundaries and appreciates the contributions ofother people We are on a journey to create the best Infineon for everyone. We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. Our hiring decisions are based on skills and experience. Even if you don't meet every requirement, we encourage you to apply. Please let your recruiter know if you need any accommodations during the interview process. Learn more about our various contact channels and about Diversity & Inclusion at Infineon.