QPU Integration Engineer (Assembly & Characterization focused) (f/m/d)

eleQtron develops and operates full-stack quantum computers based on trapped-ion technology. Quantum computing is a new computing paradigm rapidly approaching commercial viability. Our unique approach combines laser-cooled trapped ions with microwave control and tailored magnetic fields. Our next-generation computing machines under development will be able to find solutions to problems that are out of reach today, thus enabling new innovative products and services for a brighter future.

We are looking for a Senior QPU Integration Engineer (Assembly & Characterization focused).You will be a lead technical expert in our QPU Development team, driving the post-fabrication physical integration, advanced packaging, and end-to-end characterization of next-generation quantum processor architectures. In this pivotal role, you will serve as the primary bridge between chip design teams and cleanroom execution. You will own chip-level packaging, assembly modules, and characterization test flows, leading R&D activities within our internal cleanroom facility while managing strategic assembly and testing projects with external foundry and packaging partners.

Responsibilities:

• Serve as the Subject Matter Expert (SME) for advanced chip assembly and back-end packaging processes (e.g., precision dicing, flip-chip bonding, wire bonding, 3D interconnects, substrate integration, and cryogenic packaging stacks).

• Develop and optimize robust, high-yield packaging flows for fragile, high-value quantum hardware while minimizing mechanical, thermal, and electrostatic stress.

• Define, standardize, and execute multi-scale characterization protocols across wafer-level, die-level, and post-packaging stages (e.g., physical inspection, electrical probing, optical/metrology mapping, and cryogenic pre-screening).

• Feed metrology data, yield metrics, and structural/electrical defect density mapping back into process and design iterations.

• Collaborate closely with QPU designers, thermal/RF modeling engineers, and fab specialists to establish design-for-assembly (DFA) and design-for-testability (DFT) guidelines.

• Translate chip architectures into actionable assembly tolerance stacks, wire-bonding maps, and pinout/interconnect specs

• Take the lead in managing daily internal cleanroom assembly and test workflows, scheduling runs, setting baseline packaging procedures, and resolving real-time hardware deviations

• Oversee internal R&D projects to qualify novel packaging materials, interconnect schemes, and non-destructive inspection/testing techniques.

• Drive project management and technology transfer with external commercial packaging foundries, assembly OSATs, and research partners.

• Manage out-of-house assembly lines, wafer-to-wire-bond delivery schedules, yield matching, and subcontractor deliverables.

• Lead Root Cause Analysis (RCA) and Failure Mode and Effects Analysis (FMEA) for packaging failures, bond wire degradation, thermal mismatch issues, or low yield during characterization.

• Maintain Statistical Process Control (SPC) for critical dimensional tolerances, bond strengths, and physical defect counts across internal and external lots.

• Mentor test engineers, assembly technicians, and junior staff on advanced micro-assembly, ESD handling, cleanroom protocols, and automated data collection.

• Author comprehensive assembly documentation, SOPs, packaging roadmaps, and technical summary reports for executive and cross-functional teams.