- Location
- Austin, TX,US, US
- Type
- Full-time
- Department
- Engineering
- Education
- PhD
- Source
- Eightfold
Description
Develop and implement test benches using SystemVerilog and UVM. Design and execute verification plans based on design specifications and architecture documents. Apply Object-Oriented Design (OOD) principles to build scalable and reusable verification components. Collaborate with cross-functional teams to define test strategies and ensure comprehensive coverage. Write and maintain scripts (Python, Perl, Shell, etc.) to automate verification flows and improve productivity. Debug and resolve complex issues in simulation and emulation environments. Contribute to the development of verification infrastructure and methodologies. Communicate effectively with team members and stakeholders to report progress, issues, and solutions. Proficiency in SystemVerilog and UVM methodology. Strong understanding of Object-Oriented Programming (OOP) and test bench architecture. Experience with scripting languages such as Python, Perl, or Shell. Solid grasp of computer architecture and digital design fundamentals. Demonstrated problem-solving skills and the ability to work independently. Excellent communication skills, both written and verbal. Ability to thrive in a fast-paced and dynamic environment. Experience with formal verification or emulation platforms. Familiarity with version control systems (e.g., Git). Exposure to SoC-level verification and constrained-random testing. Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field.
