Senior Digital Design Verification Engineer - Hardware

Verification of the digital design, golden models and micro-architecture of the SerDes IPs using advanced verification methodologies such as UVM. Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology. Responsible for understanding the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design. Write and implement test plan and thoroughly verify a design in a product shipment focused / compressed schedule. Work with architects, designers, and pre and post silicon verification teams to accomplish your tasks. Experience using random stimulus along with functional coverage and assertion-based verification methodologies a must. Experience in verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug. Expertise in bus or interconnect protocols (e.g. PCI Express, USB, SATA) a huge plus. Experience in verifying complex SerDes system, understanding mixed-signal designs, and have experience in modeling of analog circuits a huge plus.