STAFF ENGINEER , DPG GRAPHICS VERIF

Own and execute functional verification for block‑level and full‑chip designs from specification through tape‑out Develop, execute, and maintain verification plans, test strategies, and coverage models based on design specifications Architect, develop, and maintain SystemVerilog / UVM‑based testbenches, test vectors, and assertions Run directed and constrained‑random simulations and debug functional failures to root cause Drive coverage closure (functional, code, and assertion coverage) and identify verification gaps Work closely with design engineers to understand RTL, review specifications, and resolve design issues Provide verification status updates, summaries, and risk assessments to project stakeholders Collaborate with cross‑functional teams including design, validation, product engineering, and methodology teams across global sites Contribute to the development and improvement of verification tools, flows, and methodologies Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Mentor and guide junior engineers, providing technical leadership within the verification team