- Location
- Boise, ID,US, US
- Type
- Full-time
- Department
- Engineering
- Seniority
- Senior
- Source
- Eightfold
Description
Req ID:
JR114916 Senior CAD Engineer – Physical Verification
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
## Responsibilities
- Develop and maintain physical verification tools, flows, and methodologies for DRAM, HBM, NAND, and emerging memory products.
- Develop, debug, qualify, and release Siemens Calibre design rule checking (DRC) and layout versus schematic (LVS) rule decks using Standard Verification Rule Format (SVRF).
- Translate process design rules into verification checks, and define the test cases, coverage criteria, and regression methods that qualify them.
- Partner with process, design, layout, modeling, and verification teams to define signoff strategies and resolve verification issues.
- Guide design teams on verification methodologies, waivers, and debugging, and provide training, documentation, and production support.
- Evaluate EDA technologies that improve verification quality, performance, and capacity.
- Automate verification setup, execution, and reporting, including AI-assisted analysis and debugging.
- Lead technical projects and contribute to the physical verification roadmap.
## Minimum Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent.
- 5+ years of industry experience in CAD, EDA, or semiconductor design.
- Experience with DRC and LVS physical verification, IC layout, and process design rules.
- Ability to interpret design-rule requirements and resolve complex verification issues in production flows.
- Proficiency in Python and at least one additional language, such as SKILL, Tcl, Perl, C, or C++, plus Linux/Unix and shell scripting.
- Solid CMOS and VLSI fundamentals, with clear communication and practical debugging skills across global teams.
## Preferred Qualifications
- Experience developing and qualifying Calibre DRC and LVS rule decks in SVRF, using nmDRC, nmLVS, and Results Viewing Environment (RVE).
- Knowledge of layout-dependent effects and electrical rule checking (ERC), programmable ERC (PERC), antenna, and density checks.
- Experience optimizing rule-deck coverage, runtime, and memory use.
- Experience with Cadence Virtuoso, SKILL, or Cadence physical verification tools.
- Experience applying AI/ML, large language models, or agentic AI to engineering workflows.
- Experience with source control, automated testing, and release management.
- Knowledge of DRAM, HBM, NAND, or emerging memory development.
Job Profile(s):
CAD Engineer 3
Relocation Level: TBD
Before Getting Started
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