- Location
- Cork, CO,IE, IE
- Workplace
- Onsite
- Type
- Full-time
- Department
- Engineering
- Seniority
- Senior
- Experience
- 5+ years
- Education
- PhD
- Source
- Eightfold
Description
Implementation and delivery of GPU cores from RTL to GDSII Semi-custom design flow and methodology development Identifying areas for flow and process improvements Verilog and System-Verilog languages RTL synthesis using physically aware tools Design constraint management for power, timing, clocking, interfaces Formal Verification for RTL-netlist and netlist-netlist checks Clock Tree Analysis and Optimization At-least 5-7 years of experience developing methodologies for PPA improvement Basic understanding of digital design and RTL development Hands on experience with EDA tools such as Synopsys Fusion Compiler, Synopsys RTL-Architect, PrimePower,PrimeTime and Prime Closure Script writing experience in UNIX shell, Python, Perl and/or TCL Excellent interpersonal and analytical skills as well as ability to work independently Highly motivated, excellent team spirit, obsession with deliverable quality and customer oriented Education Requirements Preferred: Master's, Computer Engineering and/or Computer Science and/or Electrical Engineering Required: Bachelor's, Computer Engineering and/or Computer Science and/or Electrical Engineering Where you will be working Cork has a proud reputation as Ireland's second largest economic engine and is now one of the Top 20 location choices in Europe with 39,000 people being employed by over 170 overseas companies. There's a growing diversity in the region with people from many nationalities relocating to Cork, relishing the opportunity to work and live in a location that offers an excellent quality of life. A gateway to Europe, Cork airport provides access to almost 50 international destinations including transatlantic air routes. Equal Opportunities We are an Equal Opportunity employer; all qualified applicants will receive consideration for employment without regard to race, colour, religion, sexual orientation, gender identity, national origin, disability, veteran status, or any protected classification. Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies. Managing design goals and tradeoffs in power, performance, and area