Principal Engineer, SRAM Design

Req. ID:

JR116676 Principal Engineer, SRAM Design

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Micron is seeking an experienced Principal SRAM Design Engineer to develop high-performance memory IP and testchip content for advanced semiconductor technologies.

The engineer will contribute towards architecture definition, transistor-level circuit design, simulations, and verifications.

The role requires strong hands-on knowledge of SRAM and bitcells, sense amplifiers, address decoders, control logic, etc.

The successful candidate will work closely with layout, CAD, process integration, testchip, and other partner teams to deliver robust, production-ready memory solutions.

# Key Responsibilities

• Design, Develop and verify memory-array subsystems including bitcell arrays, precharge and equalization, sense amplifiers, write drivers, address decoders, wordline drivers, control logic, etc.

• Evaluate bitcell and peripheral-circuit stability, performance, leakage, dynamic power, and area across process, voltage, temperature, mismatch, and aging conditions.

• Own transistor-level simulation and signoff using Spectre/FineSim, or comparable tools, including PVT corners, Monte Carlo analysis, parasitic-aware post-layout simulation, and waveform/debug reviews.

• Partner with layout engineers on floorplanning, bitcell-array composition, matching, critical-net routing, clock and control distribution, parasitic reduction, and layout-dependent effects.

• Develop or improve automation for simulation setup, corner execution, results extraction, validation, and regression using Python, Tcl, Perl, SKILL, or similar languages.

• Plan and support SRAM testchips, including memory-instance selection, PPA objectives, test access, measurement structures, characterization plans, and alignment with process-learning goals.

• Engage process and foundry partners to understand device behavior, variation, layout restrictions, reliability constraints, and technology-specific opportunities affecting SRAM design margins.

• Create clear circuit specifications, design-review material, verification plans and release documentation with traceable assumptions and decisions.

• Mentor engineers on memory-circuit fundamentals, simulation discipline, PPA analysis, debug methods, and reusable design practices.

• Explore AI-assisted engineering workflows for specification extraction, circuit and block partitioning, test-mode enrichment, design-flow automation, regression analysis, and documentation while maintaining human technical review.

# Technical Scope

• SRAM and register-file architectures, bitcell arrays, local and global datapaths, sensing, write paths, decoding, control, clocking, test access, and retention behavior.

• Low-power and high-performance design techniques including assist circuits, biasing, leakage reduction, dynamic-power optimization, robust low-voltage operation, and variation-aware sizing.

• Memory compilers and configurable macro generation, including architecture templating, legal configuration space, multi-view collateral, validation, and customer or SoC integration support.

• Circuit verification using spice simulators, PVT analysis, Monte Carlo mismatch, extracted post-layout simulation, and timing/power model correlation.

• Testchip development, silicon data analysis, debug, model calibration analysis, and process integration collaboration.

# Minimum Qualifications Demonstrated industry experience of 8+ yars in SRAM, register-file, ROM, DRAM peripheral, or other custom-memory circuit design.

• BS/MS/PhD in Electrical Engineering, Electronics, VLSI, Microelectronics, Computer Engineering, or a related field.

• Strong knowledge of CMOS transistor-level circuit design, memory architecture, static and dynamic timing behavior, power analysis, signal integrity, and process variation.

• Hands-on experience with Cadence Virtuoso and SPICE-class simulators such as HSPICE, Spectre, or FineSim.

• Experience performing PVT-corner, Monte Carlo, parasitic-aware post-layout, and power/timing characterization analyses.

• Ability to translate product or testchip requirements into circuit architecture, measurable design targets, verification plans, and release criteria.

• Experience collaborating with layout, CAD, process/foundry, verification, product, and silicon characterization teams.

• Clear technical communication, structured problem solving, and the ability to debug complex circuit or silicon issues using data and waveform evidence.

# Preferred Qualifications

• Experience developing low-power SRAM compilers or register-file compilers across multiple technology nodes and foundries.

• Experience with bitcell and peripheral circuit stability analysis, PPA aware design schemes, and memory validation.

• Track record of taking memory IP from product definition and circuit design through layout, simulations, release, and silicon correlation.

• Experience planning memory testchips and partnering with silicon test teams on characterization, debug, and correlation.

• Proficiency in Python, Tcl, Perl, SKILL, or similar languages for simulation, characterization, regression, and design-flow automation.

• Familiarity with RTL-to-GDS or digital-on-top methodologies for memory periphery and control logic, alongside full-custom array and critical-circuit design.

• Experience applying agentic AI, coding assistants, or custom LLM agents to specification processing, design automation, validation, or engineering productivity.

Job Profile(s):

Semiconductor Design Engineer 5

Relocation level: (TBD)

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