- Location
- Santa Clara, CA,US, US
- Type
- Full-time
- Department
- Engineering
- Seniority
- Senior
- Source
- Eightfold
Description
Own the package‑level reliability spec for assigned products Define qualification requirements and pass/fail criteria for device/package‑level reliability (e.g., HTSL, TCT, UHAST, pre‑conditioning, JESD22 methods) and Package‑on‑board / board‑level reliability (thermal cycling, shock/vibration, connector/cage interactions) Leads materials and stackup selection (substrate, solder alloy, underfill, mold, lid, TIM, etc.) and DFR trade‑offs for new packages and 2nd sources Evaluates thermo‑mechanical and SI/PI impact of those choices Analyzes qual and stress data (including HTOL, package qual, SLT/system stress) and convert to design / process/ material changes for next revision. Understands how the component FIT rolls up from component level to system level and overall availability requirement Experience with BGA/FCBGA, 2.5D/3D integration, HBM or similar high power, high pin count packages Experience with data center or cloud hardware and understanding of: Rack and cluster‑level availability targets and constraints.
