Hiring.Camp

Lead Design Verification Application Engineer

Cadence Design

·

Today

Salary
$103k – $191k
Location
SAN JOSE 09, United States of America
Type
Full-time
Department
Engineering
Seniority
Lead
Experience
3+ years
Education
PhD
Source
Workday

Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

At Cadence, we hire and develop innovators and leaders who want to make an impact on the world of technology.
We offer amazing opportunities to grow, no matter where you are in your career. The ideal candidate will be energetic, innovative and enthusiastic about how to help customers solve their toughest verification problems using Cadence technology. Join our elite application engineering team for verification to work closely with the best AEs, PEs and R&D in EDA at a company listed in Fortune magazine and Great Place to Work as one of the World's Best Workplaces™ year after year!
As an integral member of the North America Verification Field Applications Engineering (AE) team, you will work directly with industry leading semiconductor and system companies to deploy Cadence’s market leading verification platforms including cutting edge technologies using AI assistants, Agentic AI and machine learning. In this customer facing role you will provide the front line technical support in the pre and post-sales process and will work with team members to come up with innovative solutions to address our customers’ most challenging problems in verification. You will own customer success!
As part of the team, you will develop customer specific verification requirements, including advanced verification component development, methodology support, and operation and maintenance of Cadence’s verification tools and services. You will support technical evaluations and benchmark development for Cadence’s market leading tools such as Xcelium simulation platform and Verisium platform of AI and ML tools for enhanced verification. You will create and conduct technical presentations and product demonstrations for customers.
At Cadence, customers are at the heart of everything we do. Talented engineers like you are what enable us to materialize this passion into results. By working directly with Cadence R&D and driving customer engagements, you will enhance your in-depth knowledge in verification tools, unlock unique expertise in verification methodologies, and level up your communication, customer, and sales skills. No matter where you are in your career, whether your next career step is to stay on the technical track, move up in management, or explore sales/marketing career opportunities, the skills and expertise you gain as an Application Engineer here at Cadence will put you miles ahead in your career advancement.

Key Responsibilities:

- Establish technical credibility and rapport with the customer
- Work closely with an experienced team to become the go-to expert for technical inquiries and support for verification platforms
- Become part of a team that provides in-depth technical assistance in collaboration with R&D to help support advanced verification flows and AI/ML applications to secure design wins
- Champion the customer needs and work with R&D and marketing to develop competitive and creative technical solutions
- Learn the competitive landscape and continuously work on differentiating Cadence’s solutions
- Write technical product literature such as application notes and technical articles

Requirements:

Minimum:

- BS, MS, or PhD degree in Computer Science/Engineering, Electrical Engineering, or related field

- 3+ years experience with SystemVerilog, VHDL, Verilog

- Good understanding and knowledge of Object Oriented Programming and experience in one such programming language such as C++, Java, Python or SystemVerilog
- Knowledge of Linux/Unix platforms and scripting languages such as Perl, Tcl, Python
- Strong verbal and written communication skills
- Self-motivated and strong teamwork skills
- Strong problem solving skills

Preferred:

- Experience with simulation, functional verification, testbench creation and debug
- Education or experience in Verilog/SystemVerilog
- Education or experience in C/C++/SystemC
- Knowledge of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing
- Digital design or digital verification experience

The annual salary range for California is $102,900 to $191,100. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Skills

PythonJavaPerlLinuxMachine Learning

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