Senior Engineer, Physical Design Engineering (ASIC)

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.

          

About the Role

As a Senior Physical Design Engineer, you will play a key role in the implementation and delivery of complex digital and mixed-signal IC designs. You will work across the physical design flow, from floorplanning through place-and-route, timing closure, physical verification, and tapeout support, helping turn architectural and RTL intent into robust silicon implementation. This role requires strong technical depth in physical design, the ability to solve complex implementation challenges, and effective collaboration with cross-functional teams across the development cycle.

Key Responsibilities

• Own physical design implementation for complex digital blocks and subsystems, including floorplanning, placement, clock tree synthesis, routing, and physical optimization
• Drive timing closure, congestion analysis, power optimization, and area improvement across assigned blocks or subsystems
• Perform physical verification activities including DRC, LVS, ERC, and reliability checks in collaboration with relevant teams
• Develop and refine physical design constraints, scripts, and flow improvements to improve quality and execution efficiency
• Collaborate closely with RTL, design verification, DFT, STA, library, and package teams to resolve design and implementation issues
• Support block-level and top-level integration activities, including interface planning, timing constraint alignment, and implementation readiness
• Analyze and debug timing, signal integrity, power, and physical implementation issues across the full backend flow
• Contribute to methodology improvements and help establish best practices for physical design execution
• Participate in design reviews and provide clear technical input on implementation trade-offs, risks, and readiness
• Author and maintain documentation for design implementation, constraints, flows, and signoff status
• Mentor junior engineers on physical design practices, tool usage, and debugging approaches
• Support tapeout planning and execution activities to ensure high-quality delivery against project milestones

Must Have Skills

• Strong experience in physical design for ASIC/SoC development, including successful implementation through tapeout
• Expertise in floorplanning, place-and-route, clock tree synthesis, timing closure, and physical verification
• Strong understanding of timing analysis, constraints, signal integrity, power optimization, and physical design trade-offs
• Experience with industry-standard physical design and signoff tools, including Cadence-based flows
• Scripting experience in TCL, Python, or similar languages for automation and flow improvement
• Experience collaborating across cross-functional teams including RTL, STA, DFT, design verification, and package or product engineering
• Strong problem-solving and debug skills across backend implementation challenges
• Clear communication and technical documentation skills
• Demonstrated ability to independently drive complex blocks or major implementation workstreams

Preferred Qualifications

• Experience with advanced-node implementation and low-power design methodologies
• Familiarity with mixed-signal integration considerations and top-level implementation challenges
• Experience improving backend flows, automation, or methodology
• Prior mentoring experience or informal technical leadership on project execution

Preferred Education and Experience

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field, or an equivalent combination of education and 5+ years of related experience
• Master’s degree in Electrical Engineering, Computer Engineering, or related field, or an equivalent combination of education and 5+ years of related experience

We recognize that candidates may not meet every listed requirement. If you bring relevant experience and a willingness to learn, we encourage you to apply.

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For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

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Job Req Type: Experienced

          

Required Travel: Yes, 10% of the time

          

Shift Type: 1st Shift/Days

The expected wage range for a new hire into this position is $116,960 to $160,820.

• Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.

• This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.

• This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.