Senior ASIC Design Engineer

As a key member of the GPU Design team, you will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications. Analyze architectural trade-offs based on features, performance requirements and system limitations. Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. Collaborate and coordinate with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks. Work on a broad list of IPs such as GPU's work scheduler, time distribution system, interrupt controllers, and DMA engines. Architect features to help silicon debug and support post-silicon validation activities. Experience in micro-architecture and RTL development (Verilog), focused on arbiters, scheduling, synchronization & bus protocols, interconnect networks and/or caches.