- Location
- SHANGHAI 07, China
- Type
- Full-time
- Department
- Engineering
- Seniority
- Lead
- Source
- Workday
Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Responsibilities
- Drive low-power design and verification activities, including UPF modeling, multi-voltage domain design, and power-aware simulation/emulation
- Support customer projects on both functional verification and power validation
- Analyze and debug complex issues related to power intent, RTL design, and system integration
- Collaborate closely with global R&D teams to deliver and optimize technical solutions
- Guide customers to success by providing high-quality technical support and troubleshooting solutions
- Contribute to methodology development, knowledge sharing, and best-practice standardization
Requirements
- Bachelor’s degree or above in Microelectronics, Electrical Engineering, or related fields
- Experience in at least one of the following areas:
- Low-power design or verification (UPF/CPF/Power-aware verification)
- RTL design or verification (SystemVerilog/UVM preferred)
- Solid understanding of:
- SoC architecture and digital design principles
- Power management techniques (Power domains, Isolation, Retention, DVFS, etc.)
- Strong problem-solving and debugging skills in complex systems
- Good communication skills in English (both verbal and written), able to work in a global environment
Preferred Qualifications
- Experience with Palladium/Protium/hardware emulation platforms
- Familiarity with EDA tools and verification flows
- Customer-facing experience (AE/PE/Solution Engineer)
- Tape-out experience in SoC or ASIC projects
- Experience in power analysis and optimization
