- Location
- San Jose, California, United States
- Department
- CTO
- Seniority
- Lead
- Source
- Greenhouse
Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Objective
As the gatekeeper of IP Management, Methodology and Quality at Astera Labs, you will lead the strategic development of our AI-powered IP Lifecycle Management and IP Quality Assurance Platform. You won't just run tools; you will architect a scalable, user-friendly system that serves as the foundation for our "AI-first" IP ecosystem. Your mission is to ensure every IP, whether internal or external is easily accessible, physically, logically, and structurally "SOC-ready," preventing late-stage integration breaks that delay tape-outs. Our vision is to revolutionize IP Management and Quality Assurance with an AI-first approach.
The candidate will be responsible for developing the platform, auditing and qualifying internal and external IP (Hard/Soft Macros, PHYs, Memories and standard cells libraries among other IPs). The IPLM and IPQA tools will scale to cover SOC QA and be a key element of the tape out sign-out requirements. The successful candidate will have the right expertise to run all EDA tools, understand the results, challenge the false pass scenarios, and dig into the root cause of real errors. They will work with the vendors or with our internal IP teams to solve the issues.
They will be responsible for ensuring that all IP deliveries are integrable, timing-clean, and manufacturable, preventing "late-stage" SOC breaks caused by inconsistent IP views or structural violations. IPQA will cover all aspects of the design flow starting from Architecture coherence, PPA evaluation, Front-End integration, SDC, RDC, DFT, PD and PDV, Packaging, ESD, Waivers, IP-XACT; and be scalable from the technology foundations, FinFet and Gate-All-Around transistors’ properties, DK/PDK integrity and rule decks from foundries, Standard Cells, Memories, IP, Subsystems and SOC Quality.
Technical Responsibilities
- AI-Driven Automation: Architect and Lead the integration of agentic AI workflows into the IPLM and IPQA platform to automate IP Management, root-cause analysis of false pass scenarios and self-heal real issues.
- Chiplet Readiness: Verify IP compliance with high-speed and high-bandwidth interface standards for heterogeneous integration.
- Cross-View Consistency: Architect automated audits for logical-to-physical consistency across RTL, Liberty, LEF, GDSII, and CDL views, focusing on pin-naming, bus-integrity, and functionality.
- Physical & Sign-off Audits: Perform independent LVS, DRC, and Antenna signoffs using native runsets for 5nm/3nm and beyond nodes.
- Structural & DFT Verification: Validate DFT requirements, including scan-chain integrity, MBIST handshakes, and fault-coverage transparency.
- Power & Timing Integrity: Audit Power Domain (UPF/CPF) consistency and conduct deep-dive Liberty (.lib) audits to identify missing timing arcs or non-monotonic lookup tables. Audit IR-drop/EM (Electromigration) reports to ensure the IP won't cause localized power grid failures.
- Waiver Management: Develop rigorous, automated Waiver Audit Protocol to ensure that provider-cleared violations do not violate Astera Labs' internal sign-off deck requirements.
- Lessons learned from release to release, from generation to generation need to be tracked and checked. Responsible for making sure releases are complete; patches are integrated. Constraints are updated, and documentation reflects the updates including PPA impact.
Required Skills & Expertise
- IP & EDA Expert: Mastery of the full sign-off suite: PrimeTime, Fusion Compiler, Genus, Calibre, Innovus, IC Compiler, SpyGlass, Tessent, Liberate (/MX), PrimeSim. Cross-Tool Consistency expertise is a must.
- Advanced Scripting for Information Systems: Expert in Tcl for tool manipulation and Python for building AI-wrapper layers. Familiarity with SystemVerilog.
- Domain Depth: Deep understanding of FinFET/Gate-All-Around (GAA) properties, Electromigration (EM), and ESD rules. Deep knowledge of Liberty modeling and LEF/DEF physical formats.
- QA Philosophy: A "Detective" mindset with the ability to look past a "green" or “red” report to find false errors and rootcause real ones.
- Management skills: Ability to work with design teams and IP vendors to solve issues in a timely manner.
The base salary range is $175,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.