Senior Foundry Development Engineer

Senior Foundry Development Engineer – Dielectric Waveguide

Menlo Park, CA

Development Engineer – Semiconductor Materials

About our client

The Client is a venture-backed start-up company that develops high-speed interconnect links using ASICs over dielectric waveguides. We work closely with substrate vendors, foundry partners, cable and packaging subcontractors to move these products from development into manufacturing.

Position Summary

The Client is seeking a Senior Foundry Development Engineer with 10+ years of semiconductor fabrication experience and deep expertise in dry etching. This engineer will own a dielectric waveguide development process from material selection to process development and lead the transfer of qualified processes to internal fabs and external foundries. The role works closely with our Client's teams covering product development, packaging, and foundry interface.

This role will combine fundamental electrical engineering, surface science and materials science knowledge with hands-on experimentation. A successful candidate will develop hypotheses, design and execute experiments, work with internal and external fabrication facilities, and translate experimental observations into actionable improvements to performance.

Our ideal candidate is a scientifically curious, highly analytical individual who enjoys developing new processes with partners, seeking out an interaction that meets not only the engineering specifications but the business partnership objectives. The candidate should thrive in a startup environment, be self-motivated, be adaptable, and work well with teams.

Key Responsibilities

• Develop, optimize, and document semiconductor etch processes (RIE, Bosch and cryogenic) for high-aspect-ratio semiconductor structures, controlling etch rate, mask selectivity, profile angle, sidewall scalloping, uniformity, and aspect-ratio-dependent etching (ARDE).
• Characterize and mitigate etch-induced surface and subsurface damage, including sidewall roughness, notching and footing at buried layers, fluorocarbon polymer residue, and plasma-induced lattice damage.
• Define post-etch treatments and work with a broader team to verify their effect on downstream metrics.
• Establish metrology and inspection methods, including SEM cross-sections, AFM, profilometry, and optical inspection, and correlate surface condition with electrical and RF test results.
• Identify, evaluate, and develop foundry partners, assessing technical capability, capacity, quality systems, and cost against our clinet's product roadmap.
• Build long-term business partnerships with foundries and suppliers, structuring development, qualification, and supply engagements that align with both parties' technical and commercial objectives.
• Lead process transfers to outside foundries: write process specifications and travelers, define acceptance criteria and SPC limits, support qualification lots, and resolve yield excursions.
• Serve as the technical point of contact for foundry and equipment partners, review vendor data, assess partner capability, and drive corrective actions.
• Hold regular technical and business reviews with partners to track performance, align roadmaps, and resolve issues before they affect schedules.
• Apply DOE, SPC, FMEA, and structured root cause analysis to process development and sustaining work.
• Maintain process documentation and train colleagues and partner engineers on DRIE best practices.

Required Qualifications

• Master’s degree in Electrical Engineering or Materials Science, ideally a PhD.
• 10 or more years of hands-on silicon fabrication process engineering in a cleanroom environment.
• Demonstrated expertise in semiconductor etching process development and tuning on production-class platforms.
• Working knowledge of etch surface damage mechanisms, their characterization, and their mitigation, including how sidewall and surface condition affects downstream processing and device performance.
• Familiarity with lithography, wet chemical cleaning, thermal oxidation, and semiconductor cleanliness and contamination control.
• Proficiency with DOE, SPC, and failure analysis methods.
• Clear written communication, including process specifications and technical reports.

Preferred Qualifications

• Track record of transferring processes to outside foundries or high-volume fabs, from specification and qualification through ongoing yield support.
• Experience with through-silicon vias (TSVs), silicon interposers, MEMS, or SOI-based structures.
• Exposure to RF, millimeter-wave, or THz devices, including dielectric waveguide structures.
• Familiarity with wafer bonding, thinning, and dicing processes.

Skills and Attributes

• Works independently and owns problems from root cause through resolution.
• Makes decisions from data and explains the reasoning to both technical and non-technical audiences.
• Builds productive working relationships with external partners while holding them to agreed specifications.
• Comfortable in a small, fast-moving team where priorities shift between development and manufacturing support.