Principal Engineer - Verification

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Job Description:

As a Principal PCIe Verification Engineer, you will be a key member of the PCIe verification team. You will contribute to the verification strategy and technical execution for advanced PCIe protocols (Gen6 and beyond). You will design robust, scalable testbench architectures and collaborate with team members to deliver project milestones. You will also bring modern AI tools and methodologies into the verification workflow to improve productivity and help deliver high-quality, silicon-ready designs.

Key Responsibilities:

• Contribute to the verification strategy and technical execution for advanced PCIe protocols.
• Design robust, scalable testbench (TB) architectures and author comprehensive verification plans.
• Develop functional coverage models and write complex system assertions to ensure design quality.
• Collaborate as a key member of the verification team to achieve project milestones.
• Integrate modern AI tools and methodologies into the verification workflow to improve productivity.

Requirements/Qualifications:

Required Qualifications

• Bachelor's/Master's degree in Electronics/VLSI Engineering with 8–12 years of industry experience in front-end verification.
• Deep theoretical knowledge and hands-on experience with PCIe Gen6/7 and subsequent generations.
• Mastery of SystemVerilog, Verilog and UVM-based testbench development.
• Strong knowledge of AMBA protocols, preferably AXI.
• Strong foundation in digital electronics and core verification concepts.
• Hands-on experience with any of the Cadence, Synopsys or Avery VIPs.
• Hands-on experience with any of the Cadence, Synopsys or Siemens simulators.
• Exceptional logical thinking, analytical and problem-solving skills.
• Proven ability to learn rapidly and adapt to evolving technologies and project requirements.
• Excellent written and verbal communication and documentation skills.

Preferred Qualifications

• Experience with formal verification methodologies.
• Familiarity with diverse advanced verification tools and techniques.
• Experience with other high-speed serial protocols.

Travel Time:

0% - 25%

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