Hiring.Camp

Senior Principal Engineer -RTL

Marvell

·

May 14, 2026

Location
IN - Bangalore, India
Department
Engineering
Seniority
Senior
Experience
18+ years
Education
PhD
Source
Workday

Description

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Marvell's semiconductor solutions are the essential building blocks of the data
infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
The Custom and Compute Solutions Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up.

What You Can Expect

Work as Sub-system Architect on the end-to-end subsystem architecture optimized
for reuse across product lines and ease of integration.
• Own the future roadmap and execution of the subsystem, standards adoption, and
architectural trade-offs.
• Define and drive KPI’s (performance, power, security, scalability, compliance) and
make technical trade-offs to meet quality.
• Work with third party vendors (Synopsys, ARM) to define customization,
requirements and IP roadmap.
• Own and partner on the definition and delivery of subsystem collateral:
o Architecture specs and PRDs
o Integration guides and reference designs
o Performance models, benchmarks, and limits
o Verification strategy at subsystem level
• Work with the verification team on reviewing the verification test plans, verification
methodologies, full-chip simulation and emulation, performance and power
analysis and debug.
• Work closely with SoC Chief Engineers, Product Architecture, PD, DFT, FW/SW, and
System teams.
• Provide mentorship to the more junior team members.

What We're Looking For

Bachelor's degree in Computer Science, Electrical Engineering or related fields and

20+ years of related professional experience.

Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 18+ years of experience.

Experience in creating architectural, micro-architectural, and register

specifications.

Verilog/System Verilog RTL coding with System Verilog assertions

Well-versed in all stages of the ASIC design flow (including specification,

architecture and design implementation, prototype bring-up)

Has worked on complex chips such as network processors, CPUs, GPUs, NOCs,

Switches, Machine Learning SoCs etc. owning subsystem and block level

architecture and design

Strong experience with peripheral interface IPs and protocols including I3C, I2C,

SPI/QSPI, UART, GPIO, and USB standards.

Experience with third-party IP integration from vendors such as Synopsys, Cadence and ARM, including customization and subsystem integration

Experience with interconnect fabrics such as Arm and Arteris fabrics, AXI/APB

protocols, and NoC architecture

Experience with scripting in Perl/Python/Shell and extensive usage of AI agents and tools.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

#LI-CP1

Skills

PythonPerlMachine LearningCompliance

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Senior Principal Engineer -RTL at Marvell | Hiring.Camp